The invention relates to a code generator with a plurality of storage elements connected in a code-producing series, e.g., flip-flops, wherein the output of the last storage element in the series is linked with the input of the first storage element in the series to form a circuit, and outputs and inputs of the storage elements are recursively interconnected with EXOR gates inserted.
Such code generators are used for encrypting and decrypting information via communications networks. In principle, all encryption methods utilize a code, even if the information to be coded is itself used as code. The better the code used for encryption is hidden, the more effective the encryption. The longer the code, the more difficult it is to decrypt. For example, an infinite code never has to be hidden, since it is never completely known. Any code that does not repeat prior to the end of the information to be encrypted is functionally regarded as infinite. The advantage to a functionally infinite code is that the encryption and decryption process itself can be realized in a conceivably simple manner with a single EXOR or EXNOR operation. The disadvantage to a functionally infinite code is that it cannot be transmitted; it must be generated.
There is a simple way to generate a functionally infinite code by linking the two inputs of an EXOR gate with two outputs of series-connected storage elements, e.g., a shift register, and recursively interconnecting the output of the EXOR gate with the input of the shift register.
The result is a code sequence with a maximum length ofLc=2n−1                (Lc=length of code sequence; n=number of code-generating, series-connected storage elements)bits.        
The disadvantage to this code generator is that the structure of the generator can easily be inferred from the code sequence, so that it can be regenerated with an identically designed generator. The following patents represent attempts to further encrypt these code sequences with other processes, so that they can no longer be reconstructed: US 2001033663, WO 01/05090, WO 99/22484, WO 99/16208, JP10320181, WO98/02990 and EP 0782069. The code generators disclosed in these publications share in common that resonance effects shorten the length of the produced code. There also exist a number of pseudo-random-check generators, for example those described in JP 2000-101567, JP 2001-016197, EP 1999-0913964 or EP 1997-0782069. These code generators work with variables, wherein a mathematical, nonlinear conversion algorithm is used to calculate a code sequence from these variables. This is done to reduce the ability to recalculate using high and highest mathematical functions. These systems share in common that they use a mathematical functional unit that has a multi-bit input, adjacent to which is the output variable located in a code memory, and a one-bit output, from which the serial code sequence is read out, which has a negative effect on the maximum achievable code generating speed. Another object of high and heist mathematics is to find simple solutions to complex formulas, which is why the risk of discovering a simple solution to however complex a mathematical function can never be entirely precluded, and of course cannot be weighed.
The object of this invention is to provide a device for generating the most varied and long code sequences possible, wherein the goal is to get by with the least number of circuit elements possible. The code generator is to be suited for simultaneously encrypting high-frequency binary data streams over prolonged timeframes with the use of binary bit operations, wherein even the output code is to remain secret.
In order to achieve this object, this invention essentially proceeds from a code generator of the kind mentioned at the outset, wherein at least one EXOR gate is provided, whose first input is connected with the output of a storage element located in the code-producing series, whose second input is connected with the output of another storage element located in the code-producing series, and whose output is connected with the input of the storage element following the storage element connected with the first input of the EXOR gate in the code-producing series, and that the output of a storage element located in the code-producing series is connected with the input of an inverter, and the output of the inverter is connected with the input of another storage element arranged in the series. In this case, both the structure of the code generator and the algorithm running therein are known.
However, the structure is configured in such a way that it can generate a high enough number of different codes of sufficient length as to render highly improbable the discovery of the respectively used code along with the currently produced spot in the code sequence. The code cannot be regenerated if the generator can generate so many different codes that a segment of individual code cannot be used to infer its continuation. The generator generates the code sequence at the lowest possible level of bit operations. Variables are not used as the basis for calculating the code sequences, but rather only the states of individual storage elements, e.g., flip-flops or shift registers interconnected in a series. This yields the highest possible efficiency relative to the number of used switching elements on the one hand, and to the overall length of the generatable code sequences and number of generatable different codes. In addition, this ensures that the code generator can perform at the highest possible production rate.
According to the invention, the code sequence generated by the code generator is changed by inserting another EXOR gate between two storage elements located in the code-producing series, whose one input is connected to the output of a first storage element, while the second input is supplied by the output of some other storage element located in the series, and, finally, the input of the storage element connected to the first storage element in the conducting direction of the series is supplied with the output of the EXOR gate.
To generate a code proceeding from an empty storage element series that has a maximum length relative to the number of used storage elements, a single inverter must be present in the entire closed series of storage elements. The function of the inverter can of course be combined with the function of the EXOR gate in one switching element, e.g., by means of an EXNOR gate.
In order to now program different codes, the recursive function of the EXOR gate(s) is designed so that it can be enabled and disabled depending on internal code memory content. To this end, the invention is modified in such a way as to connect an AND gate in the line connecting the second input of the at least one EXOR gate and the output of the other storage element located in the code-reproducing series, so that the output of the AND gate is connected with the second input of the EXOR gate, the first input of the AND gate is connected with the output of the other storage element located in the code-producing series, and the second input of the AND gate is connected with the output of a storage element used for programming purposes.
The state of the respective storage element used for programming purposes hence determines whether the respective EXOR gate is enabled or disabled. As a consequence, such a storage element is referred to as a code-programming storage element.
To make the code more variable, a plurality of EXOR gates is preferably provided, whose first input is supplied by a respective output of one of the storage elements located in the code-producing series, and whose second input is supplied by the respective output of another storage element located in the code-producing series, which is spaced a number of storage elements in the conducting direction of the series away from the storage element respectively connected with the first input, which respectively corresponds to a different prime number that is greater than 1 and does not constitute a partial amount of the overall number of series-connected storage elements.
As a result, the resonance effects do not shorten the length of the produced code. In this case, a corresponding structure for the integration of varying code-changing EXOR gates ensures that no such partial sections of the storage element series that make up a percentage or multiple of another partial section or the entire section of the circuit exist between the two storage elements, which are situated in the code-producing series comprising a closed circuit and have the two inputs of the EXOR gates. The most effective way to realize this is to have the number of storage elements located in these partial sections and their overall number be prime numbers.
In a preferred further development of the invention, the internal code memory content is generated in such a way that not even the user knows the content of the internal code memory. This further complicates code decryption. To this end, the design preferably incorporates a plurality of code-programming storage elements that are respectively assigned to an AND gate and an EXOR gate and connected in a code-programming series comprising a closed circuit, and provides at least one EXOR gate, whose first input is connected with the output of a storage element located in the code-programming series, whose second input is connected with the output of another storage element located in the code-programming series, and whose output is connected with the input of the storage element following the storage element connected with the first input of the EXOR gate in the code-programming series. The states of the code-changing EXOR gates are hence programmed with the AND gates from a separate storage element series, which is recursively interconnected using at least one EXOR gate, in the same way as happens in the code-producing storage element series. In this case, programming takes place by providing the code-programming storage element series with a program clock, wherein a plurality of code generators can easily be programmed to an identical code, if, as described in a preferred embodiment, the code generator has at least one connection for at least a second, identically structured code generator, so that both code generators can be supplied with the same program clock at the same time.
The invention further relates to a device for sending and receiving encrypted information with at least two code generators, wherein the code generators each have a connection for simultaneously supplying the code-programming storage elements of all interconnected code generators with the same program clock, so that the code-programming storage elements of all interconnected code generators simultaneously run through all possible state combinations, and are provided with the same programming when the code generators are simultaneously separated from the program clock.
In a preferred further development, the various code-programming EXOR gates are again enabled and disabled in terms of their program-influencing action by a programming storage element series comprised of additional storage elements, so that not all possible programming states need to be run through while programming, as a result of which the state of the code after programming cannot be inferred even by approximation from the programming time duration.